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| DECIMATETM Data Sheet May 1999 File Number 3368.1 Intersil HSP43220 Decimating Digital Filter Development Software Intersil DECIMATE Development Software assists the design engineer to prototype designs for the Intersil HSP43220 Decimating Digital filter (DDF). Developed specifically for the DDF, this software consists of three integrated modules: DDF Design, DDF Simulator and DDF PROM. The Design module designs a filter from a set of user specifications for the DDF. The Simulator module models the DDF's internal operation. The PROM module uses the device configuration created by the Design module to build a PROM data file that can be used to store and download the DDF configuration. Frequency response curves are then displayed showing the resulting responses in the HDF, FIR and for the entire chip using the given filter design. Figure 2 is a typical display. The user may save this frequency response data for further analysis. The design module also creates a report file documenting the filter design and providing the coefficients and setup register values for programming the device. DDF Simulator The simulator provides an accurate simulation of the device before any hardware is built. It can be used to simulate any filter designed with DECIMATE. The simulator takes into account the fixed point bus widths and pipeline delays for every element in the DDF. The simulator provides the user with an input signal which can be used to stimulate the filter. This signal is created from the options shown in Table 1. The user can select a pure step, impulse, cosine, chirp, uniform or Gaussian noise as the input signal, or a more complex signal can be generated by combining that data with an option selected from the Signal #2 column, with the combining operator chosen from the middle column. The user can also import a signal from an outside source. TABLE 1. DDF System Design The DDF consists of two stages: a High Decimation Filter (HDF) and a Finite Impulse Response (FIR) filter. Together these provide a unique narrow band, low pass filter. Because of this unique architecture, special software is required to configure the device for a given set of filter parameters. This software uses system level filter parameters (listed below) to perform the trade off analysis and calculate the values for the DDF's Configuration Registers and FIR coefficients. Design specifications are supplied by the user in terms of: 1. Input sample frequency. 2. Required output sample frequency. 3. Passband signal bandwidth. 4. Transition bandwidth. 5. Amount of attenuation allowed in the passband. 6. Amount of stopband attenuation required for signals outside of the band of interest. This information is entered into a menu screen (See Figure 1), providing immediate feedback on the design validity. The design module calculates the order of the HDF, HDF decimation required, the FIR input data rate, minimum clock frequency for the FIR, FIR order and decimation required in the FIR. The design module will then generate the FIR filter. Four different methods are provided for the FIR design: 1. A Standard FIR automatically designed by the module using the Parks-McClellan method to compute the coefficients of an equiripple (Chebyshev) filter. 2. Any FIR imported into the Design module from another FIR design program. 3. A precompensated FIR which is automatically designed by the module to compensate for the roll-off in the passband of the HDF frequency response. 4. The FIR may also be bypassed in which case the optimal HDF is designed from the user specifications. SIGNAL #1 Step Impulse COSlNE Chirp Uniform Noise Gaussian Noise OPERATION SIGNAL #2 Step No Operation Add Concatenate Multiply Impulse COSINE Chirp Uniform Noise Gaussian Noise Imported From Outside Probes are provided to select specific areas to graphically display data values, as well as save into data files for further processing. The DDF Simulator has two levels; the DDF Simulator Specification Screen and the DDF Simulator Main Screen. The Specification Screen (see Figure 3) is used to input the simulation parameters. The user selects display modes in either continuous or DECIMATEd format and data formats in either decimal or hexadecimal. The Specification Screen also provides for selection of the input signal. The simulator main screen (see Figure 4) defines the simulator test probes and displays the data values per clock cycle. The interactive simulator screen consists of the HSP43220 Block Diagram, test probes and register 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 DECIMATETM is a trademark of Intersil Corporation. DECIMATE contents. The user selects the step size of the input sample clock and also selects the probes to be monitored. The simulator will then clock through the specified number of clock cycles and display the resulting time domain response. Figure 5 shows a typical probe display. FFTs/IFETs Monarch is available separately from The Athena Group, Inc. When used with Monarch 2.0, DECIMATE becomes a full feature design environment for a DSP system. Data can easily be transferred from DECIMATE modules to the Monarch modules for further analysis. Monarch 2.0 DSP Design Software DECIMATE is fully integrated with Monarch 2.0 professional DSP design software. Monarch is a full featured DSP package with FIR lIR filter design and analysis, two dimensional and three dimensional viewing, a programmable signal/systems laboratory with 100 + DSP/Math functions, extensive fixed-point support and S System Requirements IBM PCTM, XTTM, ATTM, PS/2 computer or 100% compatible with 640K RAM running MS/PC-DOS 2.0 or higher One MegaByte of fixed-disk space with 5.25" or 3.5" floppy drive. CGA, MCGA, EGA, VGA, 8514, or Hercules Graphics Adapter. A Math coprocessor is strongly recommended. DESIGN MODULE SIMULATOR MODULE HSP43220 DDF FILTER SPECIFICATION PROM MODULE D E C I M A T E Filter File Input Sample Rate Output Rate Passband Transition Band Passband Atten Stopband Atten FIR Type : : : : : : : : PRES.DDF 33 100 5 700 1 96 STANDARD 4 330 0.6903 MHz kHz kHz Hz dB dB Design Mode : Generate Report : Display Response : Save Freq Responses : Save FIR Response : AUTO YES LOG YES YES HDF Order : HDF Decimation : HDF Scale Factor : FIR FIR FIR FIR Input Rate : 100 kHz Clock (min): 33 MHz Order : 509 Decimation : 1 FIGURE 1. FILTER SPECIFICATION MENU 2 IBM PC, XT, AT, PS/2TM are trademarks of IBM Corporation. DECIMATE HDF Frequency Response -3.2192 FIR Frequency Response -3.2201 -50.4144 Magnitude (dB) Magnitude (dB) 0 4e+06 8e+06 Frequency (Hz) 1e+07 1e+07 -33.9581 -97.6096 -71.1364 -144.804 -108.314 -192 -145.493 0 1e+04 2e+04 Frequency (Hz) 3e+04 5e+04 System Frequency Response -0.0065 -47.6682 Magnitude (dB) -95.3298 -142.991 -190.653 -238.314 0 10000 20000 Frequency (Hz) 30000 40000 50000 FIGURE 2. FREQUENCY DISPLAY 3 DECIMATE DESIGN MODULE SIMULATOR MODULE HSP43220 DDF FILTER SPECIFICATION PROM MODULE D E C I M A T E Filter File Probe Display Save Cont. Output Display Mode : : : : PRES.DAR HEX YES CONTINUOUS Input Rate : 33 MHz Output Rate : 100 kHz INPUT SIGNAL SPECIFICATION Signal Origin : Signal #1 Operator Signal #2 : : : GENERATED COSINE + GAUSS Amplitude Frequency Phase 1.00 5 kHz 0.00 Mean 0.00 StdDev 0.500000 FIGURE 3. SPECIFICATION MENU DESIGN VIEW ANALYSIS ENHANCEMENTS CONFIG OSSHELL HSP43220 DDF SIMULATOR - MAIN DDFDES DDFSIM DDFPROM 0 INIG R COMB FIR 0 0 0 0 Out_selh HIGH Out_selh LOW 0 000000 000000 Step Size : Number Samples In : Number Samples Out : FIGURE 4. SIMULATOR - MAIN MENU 1 0 0 4 DECIMATE PROBE #0 1.0999 0.9999 0.8999 0 PROBE #1 6.70E + 07 3.35E + 07 42954 0 PROBE #2 6.70E + 07 3.44E + 07 2723756 0 PROBE #3 0.9536 0.4768 0 0 PROBE #4 0.9621 0.4581 -0.0458 0 14 FIGURE 5. SIMULATOR PROBE DISPLAY 28 29 58 29 58 511.5 1023 511.5 1023 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 5 |
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